A clock tree is used to distribute a clock to flip-flops in a synchronous digital integrated circuit (IC), such as a microprocessor. A synchronous design typically requires that all flip-flops be clocked at the same time, or that their clocks have known offsets relative to each other. It is a difficult challenge to design a clock distribution network that ensures synchronicity of clock arrival times, typically requiring special purpose software and a significant amount of manual custom design and simulation. Failure to achieve required arrival times of clocks at flip-flops results in either degraded performance (longer cycle time) or outright failure (a race condition). Moreover, even if a clock distribution network achieves the required arrival times for a particular process, temperature, and voltage (PVT) corner or set of PVT corners, it is difficult or impossible to simulate all possible PVT corners. For example, a corner in which metal is thin (resulting in large metal resistance but also smaller metal capacitance) coupled with maximum channel length transistors (resulting in large gate load capacitances and slower drive strength) is not even included in most process corner simulations. A clock distribution network in which different branches have different sensitivities to this corner will exhibit differing arrival times (skew) at flip flops connected to these branches, possibly resulting in unanticipated circuit failure.